Analog IP Design Execution Manager

Intel
Full-time Santa Clara, CA other-general
Posted:
June 13, 2026
Location:
Santa Clara, CA, United States

Job Description

**Job Details:**

**Job Description:**

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes.
As an IP execution leader, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.

**This will be a technical execution manager role.**

**This IP execution leader role will be responsible for the following:**
• All aspects of the integrated IP planning, execution, and delivery from initial engagement with SOC partners, conceptual planning and tech readiness, pre-silicon execution, post-silicon validation and launch. This leader coordinates across IP domains (architecture, analog, logic, validation) and key SOC swim lanes to deliv...

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Job Overview

Job Type: Full-time
Location: Santa Clara, United States
Posted: June 13, 2026
Deadline: June 18, 2026