ASIC Engineer

This is a hybrid role with four days per week at Cisco’s Yerevan office.

**Meet the Team**

Join the Physical Design CAD & Methodology Team—a highly skilled group at the core of ASIC implementation and signoff. Our team develops, maintains, and optimizes RTL-to-GDS Physical Design flows, enabling high-quality, scalable, and repeatable silicon execution across multiple programs.

We work closely with Physical Design, STA, Power, Physical Verification, and Front-End teams to ensure robust methodologies, predictable QoR, and successful tape-outs. We are a collaborative, technically driven team that values clean design practices, automation, and continuous improvement. If you enjoy deep technical problem-solving, flow ownership, and influencing how chips get built, this is the team for you.

**Your Impact**

As a Physical Design Flow & Methodology Engineer, you will play a critical role in developing, maintaining, and optimizing block- and chip-leve...