ASIC Engineering Technical Leader

**Meet the Team**



Join the Physical Design CAD & Methodology Team—a senior technical group responsible for defining, scaling, and sustaining RTL-to-GDS Physical Design implementation and signoff methodologies across complex ASIC programs.



Our team partners closely with Physical Design, STA, Power, Physical Verification, Front-End, and Silicon Architecture teams to drive predictable QoR, fast convergence, and first-pass silicon success. We are a highly collaborative, execution-focused team that values deep technical expertise, ownership, and mentorship. If you are passionate about shaping how advanced chips are implemented and signed off, this is the team for you.



**Your Impact**



As a Physical Design Flow & Methodology Technical Leader, you will provide technical leadership in defining, developing, and maintaining scalable, signoff-robust Physical Design flows from synthesis handoff through final GDS delivery.