Co-design engineer for future computing architectures in HPC - M/F

Description de l'offre

We are looking for a co-design engineer for future computing architectures in HPC. This position, in a fixed-term contract, is based at the Nano-Innov site of Paris-Saclay, Essonne (91). 

As part of a multidisciplinary team specializing in hardware IP design and EDA tools, you will develop innovative methodologies and tools for HW/SW co-design of electronic architectures, focusing on high-performance computing (HPC) and AI systems.

 
You will leverage VPSim (virtual prototyping) and A-DECA (architecture exploration)—tools that enable HW modeling, binary SW execution, functional validation, and performance analysis in a fully virtualized environment. These tools integrate QEMU-based emulation, external models, and a Python API for performance data extraction during application execution. A-DECA further supports efficient design space exploration via optimization strategies.

This role is part of EU-fund...