[CONTRACT] UVM Verification Engineer

Job Description

Job: Verification Engineer – UVM
Location: Sweden/Remote
Duration: End of year minimum
Start Date: ASAP

A client based in Sweden is looking for an UVM verification Engineer, this will be for an initial 6-12 month contract with extensions. The role can be performed remotely.

The successful Verification engineer will be joining a team that is being newly formed within our client's offices and will help to expand on projects being worked, both new and existing within other teams. You will be involved in new and existing ASIC projects.

Skills:
- Strong background in ASIC Verification
- System Verilog/UVM
- Knowledge of IP block level verification
- Multi-clock domains
- RTL within Verilog, VHDL and/or SystemVerilog
- Used to working with complex ASIC and/or large FPGA designs