[CONTRACT] UVM Verification Engineer

Job Description

Job Title: UVM Verification Engineer
Duration: 12 months
Location: Sweden
Remote: Up to % available
Start: ASAP

Job Description

We are looking for verification engineers for the clients Machine Learning IP. At the client, verification is a crucial and integral part of the hardware development. In this role you will support the design and verification of the client’s next generation IP, using the latest methodologies and technology.

Requirements
- Strong discipline and attention to detail in ensuring effective high quality verification that minimizes bug escapes to higher levels of validation
- Coverage driven verification expertise, in high-complexity designs
- Experience in block level, top level and system level verification
- Experience in Verilog/SystemVerilog/VHDL
- Experience in the specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches
- E...