Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.


+ STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs

+ Timing analysis, validation and debug across multiple PVT conditions

+ Run Tempus for STA flow optimization and Spice to STA correlation.
+ Required Skills -

+ Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years experience

+ Physical design experience in ASIC design environment

+ Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification

+ Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.

+ Hands-on experience with STA tools - Prime-t...