Design Verification Engineer

Autsorsa | HR & BPO Solutions

Full-time Barcelona, Kingdom Of Spain Engineering

Posted:

March 02, 2026

Location:

Barcelona, Kingdom Of Spain, Spain

Job Description

                    Develop and maintain UVM-based verification environments for complex digital designs. Requires experience in SystemVerilog and UVM.
                

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Job Overview

Job Type: Full-time

Location: Barcelona, Spain

Posted: March 02, 2026

Deadline: April 11, 2026