Design Verification Engineer

Requirements:

• Bachelors or Masters degree in Electrical/Computer Engineering or related field.
• 3+ years of experience in digital design verification (semiconductor industry preferred).
• Strong understanding of digital design and RTL fundamentals.
• Proficient in SystemVerilog and UVM methodology.
• Experience with simulation tools (VCS, ModelSim, QuestaSim, Riviera-PRO).
• Familiarity with scripting languages (Python, Perl, TCL).
• Strong debugging, analytical, and problem-solving skills.
• Good communication and teamwork abilities.

Responsibilities:

• Develop and execute verification test plans for digital ASIC/SoC designs.
• Build reusable testbench components using SystemVerilog and UVM.
• Perform functional, assertion-based, and coverage-driven verification.
• Debug simulation failures and collaborate with design teams for issue resolution.
• Document verificat...