Design Verification Engineer , UCTalent

We are searching for Design Verification Lead/Manager to work onsite in Singapore. The role requires 8+ years of experience in functional verification, strong leadership, and expertise in protocols such as PCIe, Ethernet, RISC-V, ARM, SRAM at IP and system/chip level. The candidate will own verification from planning to sign-off and provide technical guidance or lead DV tasks across teams. BitSilica will support relocation , and onboarding is expected within 2 months (end of Nov 2025).

Responsibilities

• Collaborate with the design team to understand and define verification requirements for high-speed, low power digital circuit designs from definition to implementation.
• Own and be involved in all aspects of functional verification from initial test planning, test creation, debug, coverage, to sign-off closure.
• Implement verification of high-speed, low-power digital designs at IP and system level using coverage-dr...