Design Verification Manager

About the job Design Verification Manager Description As a Design Verification Manager, you are expected to carry out the following responsibilities.
Be in-charge of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
Achieve zero-defect with the best and smartest approach to the large verification space.
Requirements
Strong knowledge of SoC design principles, including IP block integration and system-level verification
Experience with test plan development, execution, and analysis
Familiarity with EDA tools and development flows for ASIC verification
Highly disciplined, quality-minded, and highly driven for excellence.
Excellent team leader and...