Digital ASIC/FPGA Designer

Delivery Manager @ Infotree | Driving Client Success

TOP MUST HAVE SKILLS:

• ASIC RTL Design
• Clock Domain Crossing (CDC) Analysis
• RTL Synthesis
• Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools
• Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog
• Knowledge of networking standards and wired communications protocols (such as Ethernet)
• Experience with scripting languages such as Python, Perl and TCL.
• Experience with Vivado Design Suite (required) or Masters degree in computer engineering/Electrical Engineering

Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer science

Seniority Level

Mid-Senior level

Employment Type

Contract

Industry

Semiconductor ...