Digital Verification Engineer - SystemVerilog, UVM, Cadence

A global niche technology recruitment firm is seeking a Mid-Senior Level engineer in Cambridge. You will manage the digital verification environment and collaborate closely with the design team to ensure compliance with specifications. Applicants should have substantial experience in digital verification and be comfortable with Cadence Virtuoso and System Verilog. The role is full-time, requiring strong communication skills and the ability to manage time effectively in a remote team setting.
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