Digital Verification Engineer (SystemVerilog/UVM)

A leading recruitment agency is seeking an experienced digital design verification engineer in Lahore. Candidates should possess a Bachelor's or Master's in Electrical/Computer Engineering and have a robust understanding of RTL fundamentals. Candidates must have expertise in SystemVerilog and UVM methodology, along with three or more years of experience in the semiconductor industry. The role involves developing verification test plans for ASIC/SoC designs, debugging simulation failures, and working collaboratively with design teams. Competitive salary and dynamic work environment offered.
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