DRAM IP Layout Engineer – Analog Design & Verification

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a skilled engineer to design and develop IP layouts for DRAM chips. Candidates should possess knowledge of analog layout design within CMOS processes and be experienced in layout verification processes.

Key responsibilities include ensuring compliance with specifications, conducting quality reviews, and collaborating with other teams. Familiarity with Cadence tools and physical verification is crucial. The role offers the opportunity to work on innovative semiconductor technology.