DRAM IP Layout Engineer — Global Team Lead

Micron Technology, Inc is looking for a DRAM Design Technology Layout Engineer in Tlaquepaque, Jalisco. You will design and develop IP layouts for DRAM chips, ensuring engineering and process-related criteria are adhered to, while collaborating globally to ensure project success.

Ideal candidates will have a Bachelor's degree in Electrical Engineering or similar, with at least 3 years of layout design experience, and expertise in Cadence tools. The position offers comprehensive benefits including medical and paid time off.