HC
Posted:
March 02, 2026
Location:
, Penang, Malaysia, Penang, Malaysia
Job Description
- Lead FPGA synthesis, implementation, and timing closure activities.
- Work on end‑to‑end development , from system specifications and architecture to RTL design and integration.
- Design using Verilog, SystemVerilog, and VHDL .
- Utilize Intel (Altera) and Xilinx FPGA toolchains (Quartus, Vivado).
- Perform simulations using VCS, ModelSim , and other verification tools.
- Develop and integrate IP‑level RTL components for complex systems.
- Use Tcl scripts to automate and integrate designs in Quartus/Vivado environments.
- Conduct linting, CDC checks , and design quality reviews.
- Work with protocols such as PCIe, AXI, and other standard interfaces .
- Perform performance profiling and design optimization .
- Define and execute de...
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Apply Now Save for LaterJob Overview
Job Type:
Full-time
Location:
, Penang, Malaysia, Malaysia
Posted:
March 02, 2026
Deadline:
April 11, 2026