HIG-HBM ENGINEERING MANAGER - LAYOUT

Req ID: JR96276 HIG-HBM ENGINEERING MANAGER – LAYOUT

Responsibilities

• Responsible for a team to design and develop critical analog, mixed-signal, custom digital block and full chip level integration support.
• Manage a team to perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Coordinate and lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environments.
• Guide junior and senior team‑members in their execution of sub‑block‑level layouts & review their work.
• Effectively communicate with global engineering teams to assure the success of layout projects.

Minimum Qualifications

• 10+ years’ experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).