Ingeniero/a Senior FPGA

GMV
Full-time Tres Cantos, Comunidad de Madrid Engineers
Posted:
June 17, 2026
Location:
Tres Cantos, Comunidad de Madrid, Spain

Job Description

You will join the receiving team to lead FPGA/SoC based hardware design projects, architecture definition, junior team mentoring and critical system optimization.

Developing functions:

  • Architecture definition
  • Coding in VHDL/Verilog
  • Advanced verification (SystemVerilog/UVM)
  • Resource optimization
  • HW/SW interfaces definition
  • Mentoring of junior engineers
  • Technical documentation.
  • WHAT DO WE NEED IN OUR TEAM?

    For this position, we are looking for hardware engineering experts with experience in FPGA development, advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim), modular/IP design, timing optimization, high speed interfaces, C++ or Rust, Python, GIT.

    Knowledge of Process Automation, signal processing, HDL coder, soft core processors, standards (DO-254, ECSS), ASIC design would be an asset.

    We will also value availabi...

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    Job Overview

    Job Type: Full-time
    Location: Tres Cantos, Spain
    Posted: June 17, 2026
    Deadline: July 27, 2026