Junior/Senior/Staff Design Verification Engineers

Location (on-site): Malaysia (Penang, Selangor) and Vietnam (Da Nang, Ho Chi Minh)

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Role Summary

We are growing and looking for self-motivated, multi-tasker, and demonstrated team-player. This position will be responsible for RTL verification, debug, functional coverage and SVA assertion development, UVM testbench development, testplan development and new verification methodology.

Key Responsibilities

•  Develop and maintain UVM-based verification environments for IP designs.

•  Create detailed test plans based on design specifications, architectural documents, and use-case scenarios.

•  Implement constrained-random testbenches, scoreboards, and monitors to validate functional behavior.

•  Perform coverage-driven verification, including:

o Functional coverage (covergroups, coverpoints)

o Code coverage (statement, branch, toggle)

o Assertion coverage (SystemVeri...