Junior/Senior/Staff Logic Design Engineers

Location (on-site): Malaysia (Penang/Selangor)

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Role Summary

Responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.

Junior level applications are also welcomed. This is an excellent opportunity for early-career engineers to grow under the mentorship of experienced professionals.

Key Responsibilities

• IP Design Responsibility

o Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.

o Ability to produce testplans to cover design requirement

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