Ca
Posted:
March 03, 2026
Location:
Bangalore, India, India
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities:- Design and integration of IPs in SoC based on high-level architectural specifications from customer.- Perfom Lint/CDC checks on the design for quality assurance and resolve issues related to the same.- Create synthesis constraints for the disign at IP and Soc level and perform basic synthesis for PPA optimization.- Create detailed Microarchitectural Specification Documents for the Design. - Provide support to verification team for test plan creation, coverage analysis and feature debug.- Provide support to physical design team as needed for implementation of design.- Use innovative solutions to automate repetitive tasks.- Collaborate within and across teams for effective project execution.
Requirements:- B.E/B.Tech/M.Tech with around 4-7 years of experience as digital design engineer.- Good knowledge of digita...
Responsibilities:- Design and integration of IPs in SoC based on high-level architectural specifications from customer.- Perfom Lint/CDC checks on the design for quality assurance and resolve issues related to the same.- Create synthesis constraints for the disign at IP and Soc level and perform basic synthesis for PPA optimization.- Create detailed Microarchitectural Specification Documents for the Design. - Provide support to verification team for test plan creation, coverage analysis and feature debug.- Provide support to physical design team as needed for implementation of design.- Use innovative solutions to automate repetitive tasks.- Collaborate within and across teams for effective project execution.
Requirements:- B.E/B.Tech/M.Tech with around 4-7 years of experience as digital design engineer.- Good knowledge of digita...
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Job Type:
Full-time
Location:
Bangalore, India
Posted:
March 03, 2026
Deadline:
April 05, 2026