Lead design verification engineer

Lead Design Verification Engineer
Location: Hyderabad, India
Experience: 5–10 Years
Role Overview
We are seeking an experienced Verification Engineer to lead the verification of complex storage and high-speed interface IPs, subsystems, and So Cs. The ideal candidate will possess deep expertise in modern verification methodologies, strong protocol knowledge, and a proven track record of delivering high-quality silicon for advanced ASIC/So C products.
Key Responsibilities
- Lead end-to-end verification of NAND, DDR, PCIe, and NVMe-based IPs and subsystems.
- Define and execute comprehensive verification strategies, test plans, and coverage closure methodologies at Block, Subsystem, and So C levels.
- Architect and develop robust, reusable UVM/System Verilog-based verification environments.
- Drive functional verification using constrained-random, assertion-based, and coverage-driven methodologies.
- Develop verification components including VIPs, scoreboards...