Lead engineer

Uni Connect
Full-time Singapore, Singapore Other-General
Posted:
March 03, 2026
Location:
Singapore, Singapore, Singapore

Job Description

Responsibilities

You will be responsible for verifying digital and mixed -signal designs, including systems -on -chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Specific responsibilities include:

  • The right candidate will be a self -starter who assumes full ownership of DV tasks and delivers high -quality results.
  • Develop test plans at block, sub -system, and chip level.
  • Execute SoC -based verification at full -chip.
  • Write C -based lib packages and tests.
  • Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
  • Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
  • Automating the test environment for randomized testing and scoreboarding.
  • Utilize advanced debugging techniques...

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Job Overview

Job Type: Full-time
Location: Singapore, Singapore
Posted: March 03, 2026
Deadline: April 12, 2026