Lead Layout Design Engineer – High-Performance DRAM

A leading memory solutions company in Tlaquepaque, Jalisco, is seeking a Layout Design Engineer. In this full-time role, you will lead and mentor engineers while designing high-performance DRAM and emerging memory products. The ideal candidate has over 5 years of experience in layout design and a solid understanding of CMOS circuit design. You will collaborate with global teams and address advanced technology challenges. Competitive compensation and growth opportunities are offered.
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