Lead RTL Design Engineer: ASIC/SoC & Digital Innovation

A technology firm based in Singapore is seeking an experienced RTL Engineer to lead design, simulation, and verification for ASIC/SoC products. The ideal candidate will have at least 5 years of experience in RTL/digital design and hold a Master's degree in Electrical Engineering. Proficiency in Verilog, SystemVerilog, and industry-standard tools is required. This role will involve mentoring junior engineers and collaborating with cross-functional teams to ensure product quality and reliability.
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