NoC Senior Design Engineer

Role Description
The input describes a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP. The engineer will own logic sub-blocks within the PHY, contribute to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.

Overview

The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.

Responsibilities

• Block Ownership and RTL Design Implementation
• Take ownership of assigned logic sub-blocks within the Memory PHY or C...