Ca
Posted:
March 03, 2026
Location:
Shanghai, China, China
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
+ To complete advanced SoC block or fullchip level implementation from RTL to GDS, including hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity and timing Signoff/ECO.
+ To well analysis and optimize timing and congestion with SDC/STA skill, advanced nodes knowledge, especial advanced CTS techniques
+ To well analysis and optimize dynamic and leakage power with advanced low power methodology and real project experience
+ To complete top level IO/bump/RDL routing and fullchip physical verification with advanced process nodes experience and Design Rule/IP/IO/STD application knowledge
+ Use Tcl/Perl/Python to write scripts to improve work efficiency
Job Description:
+ To complete advanced SoC block or fullchip level implementation from RTL to GDS, including hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity and timing Signoff/ECO.
+ To well analysis and optimize timing and congestion with SDC/STA skill, advanced nodes knowledge, especial advanced CTS techniques
+ To well analysis and optimize dynamic and leakage power with advanced low power methodology and real project experience
+ To complete top level IO/bump/RDL routing and fullchip physical verification with advanced process nodes experience and Design Rule/IP/IO/STD application knowledge
+ Use Tcl/Perl/Python to write scripts to improve work efficiency
Apply for this Job
Submit your application for the Principal Application Engineer position at Cadence Design Systems, Inc..
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Job Type:
Full-time
Location:
Shanghai, China
Posted:
March 03, 2026
Deadline:
April 05, 2026