Principal Application Engineer

Cadence Design Systems, Inc.

Full time Shanghai, Shanghai Computer Occupations

Posted:

March 03, 2026

Location:

Shanghai, Shanghai, China

Job Description

Description
 :To complete advanced SoC block or fullchip level implementation from RTL to GDS, including hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity and timing Signoff/ECO. 
To well analysis and optimize timing and congestion with SDC/STA skill, advanced nodes knowledge, especial advanced CTS techniques
To well analysis and optimize dynamic and leakage power with advanced low power methodology and real project experience
To complete top level IO/bump/RDL routing and fullchip physical verification with advanced process nodes experience and Design Rule/IP/IO/STD application knowledge
Use Tcl/Perl/Python to write scripts to improve work efficiency
Position Requirements:
 Master with 6+ years working experience
 Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
 Requires working knowledge o...
                

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Job Overview

Job Type: Full time

Location: Shanghai, China

Posted: March 03, 2026

Deadline: April 12, 2026