Principal Engineer Analog Layout

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• Participate in block/IP/chip floor planning from scratch, performing routing & layout verification (such as LVS, DRC, Antenna & others) and troubleshooting the results
• Lead/co-lead the physical layout of IP/full chip design by working closely with cross functional team leader
• Conduct thorough layout design reviews internally & external review with circuit designers
• Plan overall project schedule and distribute tasks to project team members
• Extensive use of CAD tools (Cadence Virtuoso--VXL & Mentor Calibre) in IP/chip integration and verification
• Capable in guiding/...