Un
Posted:
February 26, 2026
Location:
Singapore, Singapore, Singapore
Job Description
- Understanding
design specification and performing RTL design of the IP using Verilog/System
Verilog - Perform design
verification, formal verification and code coverage analysis of the IP - Understanding
timing constraints to ensure that the IP passes post -layout simulation - Create clear
and precise documentation for the design - Support
post -silicon validation effort
Requirements
- Understanding
design specification and performing RTL design of the IP using Verilog/System
Verilog - Perform design
verification, formal verification and code coverage analysis of the IP - Understanding
timing constraints and applying right timing constrints - Create clear
and precise documentation for the design
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Submit your application for the RTL Design Engineer position at Uni Connect.
Apply Now Save for LaterJob Overview
Job Type:
Full-time
Location:
Singapore, Singapore
Posted:
February 26, 2026
Deadline:
April 07, 2026