RTL2GDSII

ASIC Physical Design Engineer- 3 MONTH CONTRACT

Chipright seeks highly motivated and experienced ASIC Digital Physical Design Engineer to work closely with our customer. We require an engineer to work with leading-edge EDA tools in delivering an RTL design to GDSII. This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers.

Requirements

7+ years experience in development of ASIC designs
Full RTL to GDS2 flow.
Proficient with Cadence environment
required to take several small blocks through from specification to P&R.
familiar with the P&R flow, and re-simulation with SDF back annotation.
Experience with STA 
Experience with Place & Route, Layout Finishing
Experience with Design Rule Checking (DRC) LVS and all aspects of Physical Verification
Timing constraints development
required to modify to support spec changes and testing.
Applicants with Octave or Matlab experience ...