Semiconductor Design-for-Test Engineer

Location: Singapore, Jurong East
Responsibilities:
Collaborate closely with IC Design teams at Realtek.
Engage with design team to discuss and extend specifications, particularly with respect to test insertion and test pattern generation.
Develop test plans and implement design-for-test structures (At-speed test, MBIST, test compression, boundary scan), with a strong background in hierarchical DFT flow.
Create or modify scan constraints.
Generate ATPG vectors for various fault models and scan fsdb for IR analysis.
Perform functional and ATPG pre- and post-layout simulations.
Improve the internal scripting environment based on acquired knowledge.
Requirements:
Bachelor's or Master's degree in Electrical Engineering or a related field.
Proven experience in DFT and ASIC synthesis, with a focus on design-for-test structures.
Familiarity with industry-standard EDA tools, such as Synopsys, Cadence, or Mentor Graphics.
Proficiency in scripting languages,...