Senior ASIC Design Engineer — High-Impact SoCs (Equity)

A leading technology company in Toronto is looking for a Senior ASIC Design Engineer to implement and document high-performance RTL designs. This role involves architecture analysis and collaboration with various teams to meet design targets. The ideal candidate will have significant experience in RTL development and ASIC design flow. The position offers a competitive salary range of CAD 155,000 – 205,000 for Level 4, and CAD 195,000 – 245,000 for Level 5, along with equity and benefits.
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