Qu
Posted:
June 10, 2026
Location:
toronto, on, Canada
Job Description
Join Qualcomm Canada as a Senior ASIC Engineer specializing in RTL design. Innovate and optimize digital solutions for high-performance products in a collaborative environment.
This role in Qualcomm’s Engineering Group involves the micro-architecture and RTL design of vital SoC blocks. You'll be responsible for the overall quality checks, documentation, and synthesis constraints essential to product success. Your multidisciplinary background will enhance the design process, ensuring robust solutions.
Key Responsibilities:
• Lead RTL design and micro-architecture for SoC blocks
• Perform Lint, CDC, and LEC quality checks
• Document hardware block specifications and testing methodologies
• Debug and resolve issues uncovered by the verification team
• Create synthesis constraints to guide development
Requirements:
• Master's degree with 5+ years in ASIC design
• Expertise in RTL design using Verilog/VHDL
• Knowledge of DSP and analog design principles
•...
This role in Qualcomm’s Engineering Group involves the micro-architecture and RTL design of vital SoC blocks. You'll be responsible for the overall quality checks, documentation, and synthesis constraints essential to product success. Your multidisciplinary background will enhance the design process, ensuring robust solutions.
Key Responsibilities:
• Lead RTL design and micro-architecture for SoC blocks
• Perform Lint, CDC, and LEC quality checks
• Document hardware block specifications and testing methodologies
• Debug and resolve issues uncovered by the verification team
• Create synthesis constraints to guide development
Requirements:
• Master's degree with 5+ years in ASIC design
• Expertise in RTL design using Verilog/VHDL
• Knowledge of DSP and analog design principles
•...
Apply for this Job
Submit your application for the Senior ASIC Engineer - RTL Design Focus position at Qualcomm.
Apply Now Save for LaterJob Overview
Job Type:
Full-time
Location:
toronto, Canada
Posted:
June 10, 2026
Deadline:
July 20, 2026