Senior ASIC RTL Engineer, Core IP

Senior ASIC RTL Engineer, Core IP

_corporate_fare_ Google _place_ Bengaluru, Karnataka, India

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
+ Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP), defining design constraints (SDC) and Low-power intent (UPF).

**Preferred qualifications:**

+ Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
+ Experience with a scripting language like Perl or Python.
+ Experience in design and development of aud...