Senior ASIC RTL/SoC Design Engineer – Lead & PPA

A leading technology company based in Singapore seeks an experienced engineer to lead RTL design and verification efforts for their ASIC/SoC products. The role requires expertise in Verilog/SystemVerilog, with a solid background in both pre-layout and post-layout simulation. Responsibilities include collaborating with cross-functional teams, mentoring junior engineers, and ensuring robust designs through thorough analysis and reviews. The successful candidate will thrive in a fast-paced environment focused on innovation and growth.
#J-18808-Ljbffr