Senior ASIC Synthesis and STA Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Ciena’s next-generation Wavelogic Digital Signal Processor (DSP) programs rely on deep technical excellence, cross-functional collaboration, and continuous innovation. This role offers the opportunity to shape the frontend implementation of industry-leading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of high-performance optical networking.

How you will make an impact:

• Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain...