Senior ASIC Synthesis and STA Engineer (Ottawa)

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Make An Impact

• Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation
• Develop and maintain timing constraints to support synthesis and signoff for subsystem integration
• Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages
• Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity
• Create and optimize scr...