Senior Design Verification Engineer – RISC‑V & Crypto Cores

A leading semiconductor company in Cambridge is looking for a Senior Design Verification Engineer to drive innovation in next-gen semiconductor projects. The role involves designing and debugging system-level tests and requires strong expertise in SystemVerilog and UVM. Candidates should have at least 5 years of experience in design verification and a technical degree. Benefits include generous annual leave, pension contributions, and private medical insurance.
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