Senior Digital IC Design/Verification Engineer

My client is seeking a highly skilled and experienced Senior Digital Design and Verification Engineer to join their innovative team in Zürich, Switzerland. This role offers a unique opportunity to work on cutting-edge compute-in-memory technology, contributing to the design and verification of our digital IP portfolio. The ideal candidate will have a strong background in digital design and verification, with a focus on delivering high-quality, synthesis-ready SystemVerilog RTL and UVM environments.
Responsibilities
As a Senior Digital Design and Verification Engineer, you will:
Implement RTL for memory-mapped control blocks, AXI/AHB/APB bridges, FIFOs/scoreboards, arbiters, DMA, and datapaths, ensuring synthesis-friendly code with a clear reset/CDC strategy.
Optimise designs for power with a power-driven mindset and approach.
Develop UVM testbenches, including agents, sequencers, predictors, and scoreboards, driving constrained-random and directed testing to achieve cove...