Re
Posted:
February 24, 2026
Location:
Bengaluru, India, India
Job Description
Senior Engineer, Analog Circuit Design
Job Description
Looking for an Engineer with good understanding of basic analog blocks, exposure to power FET technology and high voltage design rules. Candidate must be passionate to learn and lead the evolving topologies in power delivery applications across wide range of market. The candidate will join the 2.6B$ Power Business Unit where he/she will get to work on a wide range of high voltage products like isolated gate driver, HV Gan power stages, LV GaN drivers and power stages, powering the next generation of servers, motor drives solar inverters, EV traction inverters and chargers. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.
**Essential Functions:**
+ Understanding of MOS, Diodes and power FETs (LDMOS) in terms of characteristics, device physics and operating mode...
Job Description
Looking for an Engineer with good understanding of basic analog blocks, exposure to power FET technology and high voltage design rules. Candidate must be passionate to learn and lead the evolving topologies in power delivery applications across wide range of market. The candidate will join the 2.6B$ Power Business Unit where he/she will get to work on a wide range of high voltage products like isolated gate driver, HV Gan power stages, LV GaN drivers and power stages, powering the next generation of servers, motor drives solar inverters, EV traction inverters and chargers. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.
**Essential Functions:**
+ Understanding of MOS, Diodes and power FETs (LDMOS) in terms of characteristics, device physics and operating mode...
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Job Type:
Full-time
Location:
Bengaluru, India
Posted:
February 24, 2026
Deadline:
March 06, 2026