Senior FPGA & RTL Design Engineer

UST
Full-time , Penang, Malaysia, Penang Engineering
Posted:
March 02, 2026
Location:
, Penang, Malaysia, Penang, Malaysia

Job Description

A technology company in Malaysia, Penang, is seeking an experienced Senior FPGA/RTL Design Engineer to design, develop, verify, and optimize digital hardware architectures for high-performance systems. The ideal candidate will have over 5 years of hands-on experience with strong proficiency in VHDL, Verilog, and FPGA design. Responsibilities include mentoring junior engineers, performing timing analysis, and collaborating with cross-functional teams to ensure seamless hardware integration. This is a key role in driving innovation within the engineering team.
#J-18808-Ljbffr

Apply for this Job

Submit your application for the Senior FPGA & RTL Design Engineer position at UST.

Apply Now Save for Later

Job Overview

Job Type: Full-time
Location: , Penang, Malaysia, Malaysia
Posted: March 02, 2026
Deadline: April 11, 2026