Senior HBM Validation Engineer - Verilog & Test Automation

A global semiconductor company in Singapore is seeking a skilled Validation Engineer to execute HBM validation tasks. The ideal candidate should possess over 5 years of relevant experience, particularly in DRAM/HBM/NAND validation, along with strong programming skills in C/C++ and Python. Responsibilities include conducting validation runs, analyzing data, and collaborating with cross-functional teams. This role offers the opportunity to work in a high-pressure, fast-paced environment with extensive technical challenges.
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