Senior Layout Engineer

Own transistor-level and block-level custom layout for mixed-signal, SRAM, and custom-digital IP that powers our compute-in-memory SRAM (ComputeRAM®). You will plan floorplans, implement device-level layouts with production-grade matching/guarding, close DRC/LVS/PEX on advanced nodes down to 4 nm and below, and collaborate tightly with custom-design, digital, and PD/STA teams to hit aggressive PPA, yield, and reliability targets. You will bridge classic analog techniques (common-centroid/interdigitation, shielding, isolation) with FinFET/FDSOI rules, multi-patterning/EUV constraints, and modern DFM practices.

What you’ll do

• Plan & implement full-custom layouts for standard cells, custom datapaths, and SRAM periphery/arrays.
• Drive and provide feedback to the design team to converge on the most power-aware design layout possible.
• Interface & integrate: align with schematic owners on constraints; define pins/abstracts, LEF views, keep-outs...