Senior / Lead Microarchitecture / RTL Engineer

Our client is expanding their RTL team and is looking for experienced Senior and Lead RTL Engineers with a strong background in RTL design and microarchitecture, ideally within RISC V based processor development.

In this role, you will contribute to the design and implementation of advanced processor components at RTL level for cutting edge technology nodes. Focus areas include the processor pipeline, d cache, i cache, L2 pipeline and custom memory controller blocks. The team values engineers who understand architectural challenges end to end and can translate them into robust RTL implementations.

Location : Barcelona, Spain - Hybrid

As a Senior / Lead Microarchitecture / RTL Engineer , your broad responsibilities will include but are not limited to:

• Design and implement RTL modules in Verilog based on architectural and microarchitecture specifications

• Contribut...