Senior Principal SOC Design Engineer

Responsibilities MaxLinear is seeking a Senior Principal SOC Design Engineer to join our VLSI group. You will be responsible for pre-silicon RTL coding of block, subsystem and top level SOC Integration. With deep understanding of design architecture and meticulous attention to details, you will develop robust and reusable Code and ensure that VHDL or Verilog implementation enables readiness for Verification, Synthesis, DfT and Low Power Insertion. In this role, your focus will be: Lead the microarchitecture definition for whole System on Chips and complex Ips in close collaboration with the architecture team Lead the front-end design activities for the integration of complex System on Chips Ensure area, performance and power targets are reached by defining best-in-class architectures and methodologies Own pre-silicon RTL Coding of block, IP and top-level SOC Integration Develop reusable RTL Code, using Generic and Modular Coding Style Contribute to verification plan from specification ...