Sy
Posted:
June 13, 2026
Location:
quebec, capitale nationale, Canada
Job Description
Enhance your career at Synopsys as a Senior Analog IC Design Engineer focused on SERDES IP. Utilize your expertise to innovate in high-speed applications and mentor fellow engineers.
At Synopsys, we're dedicated to semiconductor design excellence. We are looking for a skilled engineer with extensive experience in high-speed SERDES designs. You will work within a diverse team, mentoring colleagues and driving development in technologies that enhance customer value and improve design processes.
Key Responsibilities:
• Develop and design SERDES transceiver architectures
• Conduct high-speed analog circuit performance simulations
• Collaborate with teams to ensure design quality
• Present innovations to customers and industry groups
• Supervise physical layouts addressing parasitic issues
Requirements:
• Ph.D. with 6+ years or M.Sc. with 8+ years experience
• In-depth knowledge of CMOS design and SERDES
• Proficient in SPICE simulation and verification tool...
At Synopsys, we're dedicated to semiconductor design excellence. We are looking for a skilled engineer with extensive experience in high-speed SERDES designs. You will work within a diverse team, mentoring colleagues and driving development in technologies that enhance customer value and improve design processes.
Key Responsibilities:
• Develop and design SERDES transceiver architectures
• Conduct high-speed analog circuit performance simulations
• Collaborate with teams to ensure design quality
• Present innovations to customers and industry groups
• Supervise physical layouts addressing parasitic issues
Requirements:
• Ph.D. with 6+ years or M.Sc. with 8+ years experience
• In-depth knowledge of CMOS design and SERDES
• Proficient in SPICE simulation and verification tool...
Apply for this Job
Submit your application for the Senior SERDES Design Engineer at Synopsys position at Synopsys.
Apply Now Save for LaterJob Overview
Job Type:
Full-time
Location:
quebec, Canada
Posted:
June 13, 2026
Deadline:
July 23, 2026