Senior Verilog RTL Engineer - Core Architecture

BITDEER DEVELOPMENT PTE. LTD.

Full-time Singapore, Singapore Software Architecture & Engineering

Posted:

February 22, 2026

Location:

Singapore, Singapore, Singapore

Job Description

                    A leading technology company in Singapore is seeking an experienced engineer to implement Verilog RTL for NPU/CPU design. The role involves collaboration with hardware and software teams, focusing on architecture definition and performance optimization. Candidates should have a Master's or Bachelor's degree in relevant fields and expertise in Verilog development. The company offers an inclusive work culture, opportunities for growth, and attractive benefits.
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Job Overview

Job Type: Full-time

Location: Singapore, Singapore

Posted: February 22, 2026

Deadline: April 03, 2026