Senior/Lead SOC Formal Verification Engineer

Position Overview

We are looking for a Lead Engineer in SoC Verification to join our team and contribute to the Formal Property Verification (FPV) and Connectivity Verification of complex SoC designs.
 The engineer will be responsible for developing, executing, and maintaining formal verification strategies to ensure exhaustive property coverage, structural correctness, and architectural compliance across critical blocks and subsystems.

This role requires strong expertise in formal methodologies, hands-on experience with industry-standard formal tools, and the ability to collaborate closely with RTL design, architecture, and full-chip verification teams to ensure first-pass silicon success. The position aligns with core verification competencies expected within the organization for mid-senior technical roles. 

Key Responsibilities

Formal Property Verification (FPV) Ownership